1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a programmable data output circuit with programmable on-chip termination operations.
2. Description of the Related Art
When data is transmitted through a signal line at a data rate of over 100 bps, the larger capacitive value at output and input terminals, the more the capacitance affects the data transmitted. If the capacitance at the output terminal is large, the output driver has a low slew rate, reducing operational speed or cause erroneous data transmission. For example, if the capacitance is very large, a digital transmission signal does not fully swing and the complete signal is not received in a receiver. To solve these problems, it is most effective to reduce the capacitance as greatly as possible. However, data transmitters and receivers in an integrated circuit chip are all circuit elements directly connected with components external to the chip. To effectively drive the signals, the transmitters should have a large driving capacity, but, it is difficult to reduce the capacitance value without limit in considering protection against electro static discharge (ESD).
Generally, when signals are transferred among integrated circuits, the signal paths form transmission lines. If there is a mismatch between the transmitter, transmission line, or the receiver, the transmitted signal is reflected.
The transmission lines are therefore typically terminated with a termination device, such as a resistor with a resistance value substantially identical to a characteristic impedance of the transmission line. That is, to minimize signal reflections, ringing, overshoot and undershoot at the receiver. It is also preferable that output impedance of an output driver is matched to characteristic impedance of the transmission line as closely as possible.
If a resistor is installed for on-chip termination, the resistor dissipates power in the circuit, generates undesirable heat, and consumes power continuously even if the receiver does not receive data. Furthermore, the resistor is placed inside a chip and its value cannot be changed; therefore, it cannot adaptively carry out termination at other characteristic impedance of the transmission line.
U.S. Pat. No. 5,731,711 by Gabara, titled xe2x80x9cINTEGRATED CIRCUIT CHIP WITH ADAPTIVE INPUT-OUTPUT PORTxe2x80x9d proposes to reduce power dissipation of a chip through an adaptive on-chip termination. A controllable impedance arrangement provides different characteristic impedances through a transmission line depending on transmission and reception characteristics of data signals.
FIG. 1 is a conventional integrated circuit having adaptive input/output ports for bidirectional communication. Adaptive input/output ports 100 and 150 are disposed in the integrated circuits 101 and 151, respectively. Each adaptive input/output ports 100 and 150 includes an input buffer 105 and a controllable impedance arrangement 110 connected to a transmission line 115 through a pad 11 and an interface 103. Each controllable impedance arrangement 110 includes three switchable impedance elements 120, 125 and 130. The impedance elements 120, 125 and 130 should be switchable to provide a respective impedance value or an open circuit between respective power supply (not shown in FIG. 1) and interface 103.
In operation, each input/output port 100 or 150 can be configured to receive a communication signal from the other port by activating the impedance element 120 while deactivating the impedance elements 125 and 130. Further, each input/output port 100 or 150 can be configured to transmit a communication signal at a first signal level by activating impedance element 125 while deactivating the impedance elements 120 and 130. Likewise, each input/output port 100 or 150 can be configured to transmit a communication signal at a second signal level by activating impedance element 130 while deactivating the impedance elements 120 and 125.
However, even if different impedance values are provided respectively depending on transmission or reception to perform an adaptive on-chip termination, only one impedance may be fixedly provided, thereby rapid coordination with changing characteristic impedance values of the transmission line is difficult. In other words, for on-chip termination in reception of a data signal, the impedance element 120 is activated while deactivating the other impedance elements 125 and 130, thereby fixing the termination impedance at one value, output driver is fixed at one value for each case in performing a source termination.
Therefore, if the characteristic impedance ZO of the transmission line 115 often changes during transmitting or receiving data, it becomes difficult to match properly impedance values. Thus, a need exists for a controllable impedance circuit of an integrated circuit for effectively solving the aforementioned problems.
A semiconductor device is provided which includes: a plurality of termination circuits having a plurality of impedance elements connected to an input/output pad, said termination circuits being controlled by impedance control signals; and a controller for outputting said impedance control signals to adaptively change with changes in characteristic impedance of a transmission line connected to the input/output pad in bidirectional data communication, to adaptively control the plurality of impedance elements in the plurality of input termination circuits for matching the impedance to the characteristic impedance of the transmission line.
According to an aspect of the present invention, each of the plurality of impedance elements is configured in pairs of MOS transistors. The plurality of termination circuits have different impedance values. And each of the impedance elements of the plurality of termination circuits is independently controlled.
According to an aspect of the present invention, the controller includes: a programmable impedance controller to detect an external resistance value and to generate upper and lower driver codes as digital codes; a multiplexer to multiplex the digital codes as multiplexing outputs; and a plurality of control signal generating parts to receive the multiplexing outputs and a mode signal shifted according to transmission mode or reception mode and to generate the control signals for controlling the plurality of impedance elements. The multiplexer includes: a first group of NAND gates to generate a NAND response by receiving corresponding codes from the upper driver codes and commonly receiving the upper data output; a second group of NAND gates to generate a NAND response by receiving corresponding codes from the lower driver codes and commonly receiving the lower data outputs; a first group of inverters connected to corresponding outputs of the first group of NAND gates; and a second group of inverters connected to corresponding outputs of the second group of NAND gates. The control signal generating part comprises a plurality of inverters, NOR gates, and NAND gates to generate the control signals to control the plurality of impedance elements by receiving a mode signal shifted according to a transmission or reception mode and one of the multiplexing outputs of the multiplexer.
A method for operating the data output circuit of a semiconductor device having a plurality of impedance elements connected to an input/output pad for bi-directional data transmission through a transmission line is provided which includes the steps of: providing a variable program code signal to the plurality of impedance elements, when the semiconductor device is in data output mode, to enable the data output to perform adaptively output driving operations with transmission impedance of the plurality of impedance elements being matched to characteristic impedance of the transmission line connected to the input/output pad; and providing a variable program code signal to the plurality of impedance elements, when the semiconductor device is in data reception mode, to enable the data input from outside through the input/output pad to be shifted to an input buffer connected with the data output circuit with transmission impedance of the plurality of impedance elements being matched to characteristic impedance of the transmission line connected to the input/output pad.